1. Field of the Invention
This invention relates to process monitors for semiconductor fabrication and more specifically to a die-level process monitor (DLPM).
2. Description of the Related Art
Variations of device parameters such as transistor threshold voltage, resistance, capacitance, inductance, transconductance, and output conductance are certain to occur due to the complexity of semiconductor processing, involving energy, temperature, pressure and concentration gradients as well as geometrical and cleanliness requirements. In spite of strictly governed foundries, semiconductor processing inevitably yields a distribution of parameter values. Resulting parameter variations will affect the performance and functionality of an integrated circuit (IC). For example, typical IC designs require neighboring transistors to be virtually identical to operate properly. A slight difference in parameters in both active and passive devices reflects as an undesired output that may have critical consequences. Process monitoring is currently performed at the wafer level to verify that semiconductor processing-related parameters are within specified design limits.
Fabless companies are by definition circuit design companies that outsource the semiconductor processing to a separate manufacturing company (foundry). A foundry supplies the fabless companies with a process design kit (PDK) containing parameter values relative to their process. Fabless companies design circuits with the acceptance that the supplied PDK describes the process parameters and relative fluctuations accurately.
As illustrated in FIG. 1, the fabless company sends a design file 10, which is the circuit layout 12 of an IC 13, on a disk or via the internet to the foundry. The foundry incorporates the circuit layout to create a ‘photoshot’ 14. The photoshot 14 commonly consists of the fabless company's IC 13 as well as the foundry's own ‘test structures’ 16. The test structure 16 is placed down one side of the rectangular photoshot area. The photoshot 14 is placed repeatedly on a large round wafer 18. The test structures 16 are placed in the area of the wafer that will be consumed during the dicing process, known as the ‘scribe lines’ 20. The wafers are diced along the scribe lines into ‘die’ 22. The test structures 16 are destroyed and not a part of the final die 22.
The foundry's test structure designs consume large areas of the silicon wafer, require many area-consuming pads for I/O, require external equipment including a probe station, controllable/programmable voltage supply, current meter, ohm meter, volt meter, etc. to perform I/O, and are destroyed and rendered useless during the dicing process. Conventional test structures require external equipment to ramp the input voltage for a duration of time while measuring out the resultant current over time. The data is fed into a computer to compute the values for each device and the differences between two devices. A foundry may designate an entire wafer or specific die sites for testing and not destroy the test structures, however, these die cannot be shipped out as product to customers and are devoted for test only. Furthermore, the composition of the test structures is only known to the foundry's process engineers and thus useless to the fabless company.
It is common for the parameter fluctuations inherent to processing to cause the die not to function as designed. A customer that is supplied only with the die, does not have a means of independently determining whether the malfunction is a result of the customer's design or the foundry's manufacturing process nor can the customer gather data that may be useful for redesigning the chip, providing feedback to the manufacturer, or designing new chips.